1. Field of the Invention
The present invention relates to an array substrate for a display device and, more particularly, to an array substrate for a display device capable of minimizing a contact resistance between a pixel electrode and a metal wiring by making the metal wiring (for example, including source/drain electrode, a gate pad, a data pad, driving circuit, GIP (gate in panel) or metal wiring of ESD circuit) brought into contact with a barrier metal, and its fabrication method.
2. Description of the Related Art
In general, a metal wiring serves to relay signals to an element. The metal wiring relaying signals is low-priced and has a low resistance value, and as the metal has a strong corrosion resistance, it can contribute to high reliability and price competitiveness of a product.
In most cases, the quality of an array substrate, a first substrate, of a liquid crystal display (LCD), is determined according to which material is used for each element or according to which specification each element is designed.
For example, a small LCD device does not matter, but in case of a large-scale high resolution LCD device having a size of 18 inches or larger, a unique resistance value of materials used for gate wirings and data wirings are a key factor for determining the superiority of picture quality.
Accordingly, in case of the large-scale/high resolution LCD device, it is preferred to use a metal with a low resistance such as aluminum or an aluminum alloy as a material of the gate wirings or data wirings.
Pure aluminum has a chemically weak corrosion-resistance and a hillock (H) is generated from the surface of the gate wirings and the gate electrodes at a follow-up high temperature process. The hillock (H) may induce an abnormal growth of a gate insulating layer covering the gate wirings and the gate electrodes and cause a short circuit due to an insulation breakdown between an active layer and the gate electrode, failing to serve as a switching element.
Thus, in case of the aluminum wiring, it is used in the form of an alloy or a laminated structure is used. However, when the gate wirings are formed to be laminated, a process should be additionally performed, disadvantageously.
Recently, in an effort to avoid such problem, copper (Cu) which can be available for forming wirings through a simple process, has a low resistance and is low-priced is proposed to be used.
The related art array substrate for a display device using copper will now be described with reference to FIGS. 1 and 2.
FIG. 1 is a schematic sectional view of the related art array substrate for a display device.
FIG. 2 is a schematic sectional view of the related art array substrate for a display device, showing a copper oxide film formed on the surface where a drain electrode and a pixel electrode are in contact with each other.
With reference to FIG. 1, the related art array substrate for a display device includes gate wirings (not shown) formed to extend in one direction on a transparent substrate 11, and a data wiring (not shown) vertically crossing the gate wiring with a gate insulating layer 15 interposed therebetween to define a pixel area (not shown).
Here, although not shown, a thin film transistor (TFT) (not shown), a switching element, is formed at a crossing of the gate wiring (not shown) and the data line (not shown). The TFT includes a gate electrode 13 extending from the gate wiring, a source electrode 21 extending from the data wiring, and an active layer 17 forming a channel with a drain electrode 23 spaced apart by a certain distance from the source electrode 21. The source electrode 21 and the drain electrode 23 are made of copper (Cu) which has a low resistance and is low-priced. The active layer 17 is formed on the gate insulating layer 15 above the gate electrode 13 and formed of pure amorphous silicon layer.
A molybdenum titanium (MoTi) layer 19 is formed as a barrier metal layer between the source and drain electrodes 21 and 23 and the active layer 17. The molybdenum titanium (MoTi) layer 19 serves to prevent copper (Cu) constituting the source and drain electrodes 21 and 23 and the active layer 17 from being brought into direct contact with each other to interact.
A passivation layer 25 for protecting the TFT, the gate wirings and the data wirings is formed on the substrate 11.
A pixel electrode 29 is formed on the passivation layer 25 of the pixel area and is electrically in contact with the drain electrode 23 via a contact hole 27 formed by etching the passivation layer 25. The pixel electrode 29 is made of a transparent metal material such as ITO (or IZO).
Meanwhile, the pixel electrode is in contact with a metal wiring including the source/drain electrodes, a gate pad, a data pad, the pad portion of driving circuit, the GIP (gate in panel) or the metal wiring of ESD circuit. In the case of the metal wiring of the pad portion, not shown, a copper oxide film (Cu2O) is formed between the metal wiring and the pixel electrode, so that contact characteristics between the pixel electrode and the metal wiring is deteriorated.
As the above, the related art array substrate for a display device has the following problems.
That is, in the related art array substrate for a display device, when the pixel electrode is formed after the contact hole is formed at the passivation film, a copper oxide film (Cu2O) is generated on the drain electrode in contact with the pixel electrode due to the influence of H2O gas as shown in FIG. 2, to degrade contact characteristics between the pixel electrode and the drain electrode. Namely, the signal transferred to the pixel electrode is transferred via the source and drain data wirings. And, the copper oxide film (Cu2O) is formed between the metal wiring and the pixel electrode, so that contact characteristics between the pixel electrode and the metal wiring are deteriorated. In a situation that the same voltage is applied to the gate wirings, a current inputted to the pixel electrode is determined by resistance of the channel and resistance at the contact portion between the pixel electrode and the drain electrode.
Accordingly, although the contact resistance between the copper wiring and the pixel electrode is low, because the surface of the copper wiring is oxidized due to the processing conditions, the contact resistance is increased.
Thus, because the contact resistance between the drain electrode, the copper wiring, and the pixel electrode, is increased, when a low Vgs voltage is applied, TFT charging characteristics is not good compared with a case where a different metal such as aluminum is applied.
Thus, in the related art array substrate for a display device, the increase in the contact resistance between the drain electrode and the pixel electrode, or the contact resistance between the copper wiring (including the source/drain electrode, the pad portion of driving circuit, the GIP (gate in panel) or the metal wiring of ESD circuit) and the pixel electrode, causes a signal delay.